Generally, clock signals are required to synchronize data communication between circuits in a computing and/or in a communication device. Thus, these clock signals are ubiquitous in data processing systems and communication systems. There are also many other applications that require high speed quality clock signals. For example, radio frequency transmitters and receivers, navigation equipment and other serial link telecommunications equipment also typically requires robust clock signals. Phase locked loops, (PLL) are often utilized to generate precision clock signals from a system clock. PLLs typically have a voltage controlled oscillator (VCO) where a feedback loop controls the frequency of the VCO to provide and accurate clock output where the PLL maintains a constant phase angle relative to a reference signal. PLLs are widely used in communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.
The consumers demand for improved mobile products such as cell phones, portable computers etc., is driving the need for improved performance from these devices. One such area needing improvement is reducing the time for a device to power up or recover from a sleep mode. One component in mobile products that takes a longer time than other components to recover from a sleep mode is a PLL. Since most of devices utilize PLLs, fast locking PLLs designs have become an area of concentrated effort lately.
Accordingly, a fast locking PLL will allow a device to be able to quickly transition from a power saving “sleep mode” to a fully operational mode more quickly. One way to improve PLL lock time is by forcing the PLL to start at a frequency close to the required frequency. Generally, a PLL must be operational before other system components are activated otherwise serious failures or errors can result. One traditional method of PLL startup is to set a bias voltage of the VCO to a predetermined reference voltage that produces a startup frequency close to the target or desired frequency. Although this is a relatively simple solution, this topology has many disadvantages including a relatively slow startup.
For example, the startup frequency nearly always has to change from zero to the target frequency and the signals will often skew during this process. During the locking process, the PLL will also have to cover large frequency gaps. Some of these phenomena are due to interruptions caused by the feedback loop. Additionally, dead zone properties often occur when a PLL is close to achieving a phase-lock and such instabilities can cause an errant clock signal. Also for a significant time after startup such a configuration can create significant clock signal jitter.
Additionally, PLLs are generally required to generate different frequencies for different modes of operation, so a predetermined voltage for a predetermined startup frequency for a specific PLL cannot always be fitted to all required operational modes. Many traditional PLLs utilize a self-biased PLL architecture with “chopper circuits.” This PLL architecture suffers from long lock time because the chopper circuit reduces the speed of the VCO frequency shift during the locking process. Hence, a PLL with faster locking capacity would be useful.